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62911hkpc 20110412-s00001 no.a1953-1/27 specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. LC75839PW overview the LC75839PW is 1/4 duty and 1/3 duty general-purpose microprocessor-controlled lcd driver that can be used in applications such as frequency display in products with elec tronic tuning. in addition to being able to drive up to 208 segments directly, the LC75839PW can al so control up to 4 general-purpose output ports. because it has the pwm output of a maximum of 3 ch, the brightness control of the led backlight of rgb can be done. incorporation of an oscillation circuit helps to reduce the number of external resistors and capacitors required. features ? support for 1/4-duty 1/3-bias or 1/3-duty 1/3-bias drive techniques under serial data control. when 1/4-duty: capable of driving up to 208 segments when 1/3-duty: capable of driving up to 159 segments ? serial data input supports ccb format communication with the system controller. (support 3.3v and 5v operation) ? serial data control of the power-saving mode based backup function and the all segments forced off function. ? serial data control of switching between the segment output port and general-purpose output port function. (support for up to 4 general-purpose output ports) ? support for the pwm output function of a maximum of 3ch. (it can output from the general-purpose output port ). ? support for clock output function of 1ch. ? serial data control of the frame frequency of the common and segment output waveforms. ? serial data control of switching between the internal oscillator operating mode and external clock operating mode. ? high generality, since display data is displayed directly without the intervention of a decoder circuit. ? the inh pin allows the display to be forced to the off state. ? incorporation of an oscillator circuit. (incorporation of resistor and capacitor for an oscillation) ordering number : ena1953 ? ccb is a registered trademark of sanyo semiconductor co., ltd. ? ccb is sanyo semiconductor's original bus format. all bus addresses are managed by sanyo semiconductor for this format. cmos ic 1/4 and 1/3-duty general-purpose lcd display driver
LC75839PW no.a1953-2/27 specifications absolute maximum ratings at ta = 25 c, v ss = 0v parameter symbol conditions ratings unit maximum supply voltage v dd max v dd -0.3 to +6.5 v v in 1 ce, cl, di, inh -0.3 to +6.5 input voltage v in 2 osci, v dd 1, v dd 2 -0.3 to v dd +0.3 v output voltage v out s1 to s53, com1 to com4, p1 to p4 -0.3 to v dd +0.3 v i out 1 s1 to s52 300 a i out 2 com1 to com4, s53 3 output current i out 3 p1 to p4 5 ma allowable power dissipation pd max ta=85 c 200 mw operating temperature topr -40 to +85 c storage temperature tstg -55 to +125 c allowable operating ranges at ta = -40 to +85 c, v ss = 0v ratings parameter symbol conditions min typ max unit supply voltage v dd v dd 4.5 6.0 v v dd 1 v dd 1 2/3v dd v dd input voltage v dd 2 v dd 2 1/3v dd v dd v v ih 1 ce, cl, di, inh 0.4v dd 6.0 input high-level voltage v ih 2 osci: external clock operating mode 0.4v dd v dd v v il 1 ce, cl, di, inh 0 0.2v dd input low-level voltage v il 2 osci: external clock operating mode 0 0.2v dd v external clock operating frequency f ck osci: external clock operating mode [figure 4] 10 300 600 khz external clock duty cycle d ck osci: external clock operating mode [figure 4] 30 50 70 % data setup time tds cl, di [figure 2][figure 3] 160 ns data hold time tdh cl, di [figure 2][figure 3] 160 ns ce wait time tcp ce, cl [figure 2][figure 3] 160 ns ce setup time tcs ce, cl [figure 2][figure 3] 160 ns ce hold time tch ce, cl [figure 2][figure 3] 160 ns high-level clock pulse width t h cl [figure 2][figure 3] 160 ns low-level clock pulse width t l cl [figure 2][figure 3] 160 ns rise time tr ce, cl, di [figure 2][figure 3] 160 ns fall time tf ce, cl, di [figure 2][figure 3] 160 ns inh switching time tc inh , ce [figure 5][figure 6] 10 s
LC75839PW no.a1953-3/27 electrical characteristics for the allowable operating ranges ratings parameter symbol pin conditions min typ max unit hysteresis v h ce, cl, di, inh 0.03v dd v i ih 1 ce, cl, di, inh v i = 6.0v 5.0 input high-level current i ih 2 osci v i = v dd : external clock operating mode 5.0 a i il 1 ce, cl, di, inh v i = 0v -5.0 input low-level current i il 2 osci v i = 0v: external clock operating mode -5.0 a v oh 1 s1 to s53 i o = -20 a v dd -0.9 v oh 2 com1 to com4 i o = -100 a v dd -0.9 output high-level voltage v oh 3 p1 to p4 i o = -1ma v dd -0.9 v v ol 1 s1 to s53 i o = 20 a 0.9 v ol 2 com1 to com4 i o = 100 a 0.9 output low-level voltage v ol 3 p1 to p4 i o =1ma 0.9 v v mid 1 s1 to s53 1/3 bias i o = 20 a 2/3v dd -0.9 2/3v dd +0.9 v mid 2 s1 to s53 1/3 bias i o = 20 a 1/3v dd -0.9 1/3v dd +0.9 v mid 3 com1 to com4 1/3 bias i o = 100 a 2/3v dd -0.9 2/3v dd +0.9 output middle-level voltage *1 v mid 4 com1 to com4 1/3 bias i o = 100 a 1/3v dd -0.9 1/3v dd +0.9 v oscillator frequency fosc internal oscillator circuit internal oscillator operating mode 240 300 360 khz i dd 1 v dd power-saving mode 100 i dd 2 v dd v dd = 6.0v output open internal oscillator operating mode 800 1600 current drain i dd 3 v dd v dd = 6.0v output open external clock operating mode f ck = 300khz v ih 2 = 0.5v dd v il 2 = 0.1v dd 800 1600 a note: * 1 excluding the bias voltage generation divider resistors built in the v dd 1 and v dd 2. (see figure 1.) [figure 1] v ss to the common and segment drivers v dd 2 v dd 1 except these resistors. v dd
LC75839PW no.a1953-4/27 1. when cl is stopped at the low level [figure 2] 2. when cl is stopped at the high level [figure 3] 3. osci pin clock timing in external clock operating mode [figure 4] osci t ck l t ck h f ck = 1 t ck h+ t ck l [khz] d ck = t ck h t ck h+ t ck l 100[%] v il 2 50% v ih 2 tds v il 1 v il 1 v il 1 v ih 1 50% v ih 1 v ih 1 tch tcs tcp tdh tr tf t tds v il 1 v il 1 v il 1 v ih 1 v ih 1 50% v ih 1 tch tcs tcp tdh tr tf t
LC75839PW no.a1953-5/27 package dimensions unit : mm (typ) 3190a pin assignment 10.0 10.0 12.0 12.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (1.25) 116 17 32 33 48 49 64 sanyo : sqfp64(10x10) top view com3 s46 s47 s31 s30 s29 s28 s27 s49 s50 com2 com1 s52 s53/osci v dd v dd 1 v dd 2 v ss s51/com4 inh ce cl di s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s44 s45 s42 s43 s38 s39 s36 s37 s40 s41 s34 s35 s15 s16 s33 s13 s14 s11 s12 s8 s9 s10 s6 s7 p4/s4 s5 p1/s1 p2/s2 p3/s3 s32 s48 LC75839PW (sqfp64) 33 48 32 49 17 64 16 1
LC75839PW no.a1953-6/27 block diagram com4/s51 com3 com2 com1 s1/p1 s2/p2 s4/p4 s5 ce cl di v ss v dd 2 v dd 1 v dd inh s53/osci shift register segment driver & latch ccb interface clock generator common driver s52 control register s3/p3 s50
LC75839PW no.a1953-7/27 pin functions symbol pin no. function active i/o handling when unused s1/p1 to s4/p4 s5 to s50 s52 1 to 4 5 to 50 55 segment outputs for displaying the display dat a transferred by serial data input. the s1/p1 to s4/p4 pins can be used as general-purpose output ports under serial data control. - o open com1 to com3 com4/s51 54 to 52 51 common driver outputs the frame frequency is fo[hz]. the com4/s51 pin can be used as a segment output in 1/3 duty. - o open s53/osci 60 segment output. this pin can also be used as the external clock input pin when the external clock operating mode is selected by control data. - i/o open ce 62 h i cl 63 i gnd di 64 serial data transfer inputs. must be connected to the controller. ce: chip enable cl: synchronization clock di: transfer data - i inh 61 display off control input ? inh = low (v ss ) ...display forced off s1/p1 to s4/p4 = low (v ss ) (these pins are forcibly set to the general-purpose output port function and held at the v ss level.) s5 to s50, s52=low (v ss ) com1 to com3=low (v ss ) com4/s51=low (v ss ) s53/osci=low (v ss ) (these pins are forcibly set to t he segment output port function and held at the v ss level.) stops the internal oscillator. inhibits external clock input. ? inh = high (v dd )...display on enables the internal oscillator circuit. (internal oscillator operating mode) enables external clock input. (external clock operating mode) however, serial data transfer is possible when the display is forced off. l i gnd v dd 1 57 used to apply the lcd drive 2/3 bias voltage externally. - i open v dd 2 58 used to apply the lcd drive 1/3 bias voltage externally. - i open v dd 56 power supply pin. a power voltage of 4.5 to 6.0v must be applied to this pin. - - - v ss 59 ground pin. must be connected to ground. - - -
LC75839PW no.a1953-8/27 serial data input 1. 1/4 duty (1) when cl is stopped at the low level note: dd is the direction data. b1 b0 d2 d1 0 1 d50 p1 p0 di cl ce 0 0 1 0 1 0 0 b3 b2 a1 a0 a3 a2 d51 0 00 exf ps10 sc oc dn dt 0 0 bu p2 ps11 fc0 fc1 fc2 d52 d47 d48 d49 b1 b0 0 1 d54 d53 0 0 0 1 0 1 0 0 b3 b2 a1 a0 a3 a2 d104 d103 0 000 01 pf3 0 pf1 ps2 0 ps3 pf0 ps4 pf2 00 0 d101 d102 d99 d100 w34 b1 b0 0 1 d106 d105 w24 0 0 1 w14 1 0 0 b3 b2 a1 a0 a3 a2 d152 d151 w20 w15 w21 w23 w22 0 w35 1 w30 w25 w31 w33 w32 w13 w11 w10 w12 0000 0 d203 b1 b0 0 1 d154 d153 0 0 0 1 0 1 0 0 b3 b2 a1 a0 a3 a2 d204 0 000 01 01 0 0 0 0 0 d208 d207 d206 d205 d202 d201 d200 d199 dd 2 bits control data 18 bits display data 52 bits ccb address 8 bits dd 2 bits display data 52 bits ccb address 8 bits dd 2 bits display data 48 bits ccb address 8 bits fixed data 14 bits dd 2 bits display data 56 bits ccb address 8 bits control data 18 bits control data 22 bits
LC75839PW no.a1953-9/27 (2) when cl is stopped at the high level note: dd is the direction data. ? ccb address ......................... ?51h? ? d1 to d208 ........................... display data ? ps10, ps11, ps2 to ps4 ........ general-purpose output port (p1 to p4) function setting control data ? exf ...................................... external clock operatin g frequency setting control data ? p0 to p2 ................................ segment output port/general -purpose output port switching control data ? dt ........................................ 1/4-duty 1/3-bias drive or 1/3- duty 1/3-bias drive switching control data ? dn ........................................ s52 pin and s53/osci pin state setting control data ? fc0 to fc2 ........................... common/segment output waveform frame frequency control data ? oc ........................................ intern al oscillator operating mode/external clock operating mode switching contro l data ? sc ......................................... segment on/off control data ? bu ........................................ normal mode/powe r-saving mode control data ? pf0 to pf3 ............................ pwm output waveform frame frequency setting control data ? w10 to w15, w20 to w25,... pwm data of the pwm output w30 to w35 fc0 sc b1 b0 d2 d1 0 0 1 0 1 0 d48 d47 di cl ce b3 b2 a1 a0 a3 a2 1 0 0 d50 d49 d52 d51 0 00 p1 p0 exf ps11 dt p2 dn bu 0 0 ps10 oc fc1 fc2 pf2 b1 b0 0 0 1 0 1 0 d100 d54 d53 b3 b2 a1 a0 a3 a2 1 0 0 0 000 01 0 d104 d103 d102 d101 0 ps2 ps4 ps3 pf0 pf1 pf3 00 00 d99 w34 b1 b0 0 0 1 0 1 w10 d152 d106 d105 d151 b3 b2 a1 a0 a3 a2 1 0 0 w20 w15 w21 w23 w22 0 1 w24 w25 w31 w30 w32 w33 w35 w14 w13 w11 w12 0000 0 b1 b0 0 0 1 0 1 0 d204 d154 d153 d203 b3 b2 a1 a0 a3 a2 1 0 0 0 000 01 1 0 0 0 0 0 0 0 d208 d207 d206 d205 d202 d201 d200 d199 dd 2 bits control data 18 bits display data 52 bits ccb address 8 bits dd 2 bits display data 52 bits ccb address 8 bits dd 2 bits display data 48 bits ccb address 8 bits fixed data 14 bits dd 2 bits display data 56 bits ccb address 8 bits control data 18 bits control data 22 bits
LC75839PW no.a1953-10/27 2. 1/3 duty (1) when cl is stopped at the low level note: dd is the direction data. b1 b0 d2 d1 0 1 d50 p1 p0 di cl ce 0 0 1 d53 1 0 0 b3 b2 a1 a0 a3 a2 d51 0 d54 0 exf ps10 sc oc dn dt 0 0 bu p2 ps11 fc0 fc1 fc2 d52 d47 d48 d49 b1 b0 0 1 d56 d55 0 0 0 1 0 1 0 0 b3 b2 a1 a0 a3 a2 d106 d105 0 000 01 pf3 0 pf1 ps2 0 ps3 pf0 ps4 pf2 d107 0 d108 d103 d104 d101 d102 w34 b1 b0 0 1 d110 d109 w24 0 0 1 w14 1 0 0 b3 b2 a1 a0 a3 a2 d156 d155 w20 w15 w21 w23 w22 0 w35 1 w30 w25 w31 w33 w32 w13 w11 w10 w12 d157 d158 d159 0 dd 2 bits control data 16 bits display data 54 bits ccb address 8 bits dd 2 bits display data 54 bits ccb address 8 bits dd 2 bits display data 51 bits ccb address 8 bits control data 16 bits control data 19 bits
LC75839PW no.a1953-11/27 (2) when cl is stopped at the high level note: dd is the direction data. ? ccb address ......................... ?51h? ? d1 to d159 ........................... display data ? ps10, ps11, ps2 to ps4 ........ general-purpose output port (p1 to p4) function setting control data ? exf ...................................... external clock operatin g frequency setting control data ? p0 to p2 ................................ segment output port/general -purpose output port switching control data ? dt ........................................ 1/4-duty 1/3-bias drive or 1/3- duty 1/3-bias drive switching control data ? dn ........................................ s52 pin and s53/osci pin state setting control data ? fc0 to fc2 ........................... common/segment output waveform frame frequency control data ? oc ........................................ intern al oscillator operating mode/external clock operating mode switching contro l data ? sc ......................................... segment on/off control data ? bu ........................................ normal mode/powe r-saving mode control data ? pf0 to pf3 ............................ pwm output waveform frame frequency setting control data ? w10 to w15, w20 to w25,... pwm data of the pwm output w30 to w35 fc0 sc b1 b0 d2 d1 0 0 1 0 1 d53 d48 d47 di cl ce b3 b2 a1 a0 a3 a2 1 0 0 d50 d49 d52 d51 0 d54 0p1 p0 exf ps11 dt p2 dn bu 0 0 ps10 oc fc1 fc2 pf2 b1 b0 0 0 1 0 1 d107 d102 d56 d55 b3 b2 a1 a0 a3 a2 1 0 0 0 d108 00 01 0 d106 d105 d104 d103 0 ps2 ps4 ps3 pf0 pf1 pf3 00 00 d101 w34 b1 b0 0 0 1 0 1 w10 d156 d110 d109 d155 b3 b2 a1 a0 a3 a2 1 0 0 w20 w15 w21 w23 w22 0 1 w24 w25 w31 w30 w32 w33 w35 w14 w13 w11 w12 d157 d158 d159 0 dd 2 bits control data 16 bits display data 54 bits ccb address 8 bits dd 2 bits display data 54 bits ccb address 8 bits dd 2 bits display data 51 bits ccb address 8 bits control data 16 bits control data 19 bits
LC75839PW no.a1953-12/27 serial data transfer example 1. 1/4 duty ? when 153 or more segments are used all 288 bits of serial data must be sent. ? when fewer than 153 segments are used 216 bits of serial data shown below (the d1 to d152 display data and the control data) must always be sent. 2. 1/3 duty all 216 bits of serial data must be sent. 72 bits 8 bits d2 d1 d47 d105 1 0 0 0 1 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d48 d49 d50 d51 0000 ps11 fc0 exf p0 p1 p2 dt dn fc1 fc2 oc sc bu 0 0 1 0 0 0 1 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d53 1 0 0 0 1 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d106 d54 d99 d100 d101 d102 d151 d152 00000000000 ps2 ps3 ps4 pf0 pf1 pf2 pf3 0 ps10 1 w10 w11 w12 w13 w14 w15 w20 w21 w22 w23 w24 w25 w30 w31 w32 w33 w34 w35 0 1 d52 d103 d104 d153 1 0 0 0 1 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d154 d199 d204 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0000 d208 d207 d206 d205 d203 d202 d201 d200 72 bits 8 bits d2 d1 d47 d109 1 0 0 0 1 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d48 d49 d50 d51 d53 d54 00 ps11 fc0 exf p0 p1 p2 dt dn fc1 fc2 oc sc bu 0 0 1 0 0 0 1 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d55 1 0 0 0 1 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d110 d56 d101 d102 d103 d104 d155 d156 d107 d108 000000000 ps2 ps3 ps4 pf0 pf1 pf2 pf3 0 ps10 1 w10 w11 w12 w13 w14 w15 w20 w21 w22 w23 w24 w25 w30 w31 w32 w33 w34 w35 0 1 d52 d105 d106 d157 d158 d159 0 72 bits 8 bits d2 d1 d47 d105 1 0 0 0 1 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d48 d49 d50 d51 0 0 00 ps11 fc0 exf p0 p1 p2 dt dn fc1 fc2 oc sc bu 0 0 1 0 0 0 1 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d53 1 0 0 0 1 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d106 d54 d99 d100 d101 d102 d151 d152 0 0 000000000 ps2 ps3 ps4 pf0 pf1 pf2 pf3 0 ps10 1 w10 w11 w12 w13 w14 w15 w20 w21 w22 w23 w24 w25 w30 w31 w32 w33 w34 w35 0 1 d52 d103 d104 0 0 0 0
LC75839PW no.a1953-13/27 control data functions (1) ps10 and ps11, ps2 to ps4 ? general-purpose out put port (p1 to p4) function setting control data these control data bits set the general-purpose output function (high or low level output), clock output function or pwm output function of the p1 output pin, and the general-purpose output function (high or low level output) or pwm output function of the p2 to p4 output pins. however, be careful of being unable to set a pwm output function when the external clock operating frequency is set the f ck 2=38[khz] typ (exf="1") in external clock operating mode (oc= "1"). ps10 ps11 general-purpose output port (p1) function 0 0 general-purpose output function (high or low level output) 1 0 clock output function (clock frequency : fosc/2, f ck /2) 0 1 clock output function (clock frequency : fosc/8, f ck /8) 1 1 pwm output function (support for pwm data w10 to w15) ps2 general-purpose output port (p2) function 0 general-purpose output function (high or low level output) 1 pwm output function (support for pwm data w20 to w25) ps3 general-purpose output port (p3) function 0 general-purpose output function (high or low level output) 1 pwm output function (support for pwm data w30 to w35) ps4 general-purpose output port (p4) function 0 general-purpose output function (high or low level output) 1 pwm output function (support for pwm data w10 to w15) (2) exf ? external clock operating frequency setting control data this control data sets the operating frequency of the external clock which input into the osci pin, when the external clock operating mode (oc=?1?) is set. however, this cont rol data is effective only when external clock operating mode (oc= "1") is set. exf external clock operating frequency f ck [khz] 0 f ck 1=300[khz]typ 1 f ck 2=38[khz]typ
LC75839PW no.a1953-14/27 (3) p0 to p2 ? segment output port/general-purpose output port switching control data these control data bits switch the segment output port/general-purpose output port functions of the s1/p1 to s4/p4 output pins. control data output pin state p0 p1 p2 s1/p1 s2/p2 s3/p3 s4/p4 0 0 0 s1 s2 s3 s4 0 0 1 p1 s2 s3 s4 0 1 0 p1 p2 s3 s4 0 1 1 p1 p2 p3 s4 1 0 0 p1 p2 p3 p4 note: sn (n=1 to 4): segment output ports pn (n=1 to 4): general-purpose output ports note: when are setting (p0,p1,p2)=(1,0,1), (1,1,0), and (1,1,1), the all p1/s1 to p4/s4 output pins selects the segment output port. the table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports. correspondence display data output pin 1/4 duty 1/3 duty s1/p1 d1 d1 s2/p2 d5 d4 s3/p3 d9 d7 s4/p4 d13 d10 for example, if the circuit is operated in 1/4 duty and the s4/p4 output pin is selected to be a general-purpose output port, the s4/p4 output pin will output a high level when the display data d13 is 1, and will output a low level when d13 is 0. (4) dt ? 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data this control data bit selects either 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive. dt drive scheme the com4/s51 pin state 0 1/4-duty 1/3-bias drive com4 1 1/3-duty 1/3-bias drive s51 note: com4: common output s51 : segment output (5) dn ? s52 pin and s53/osci pin state setting control data this control data bit sets state of the s52 pin and the s53/osci pin. number of display segments pin state dn 1/4 duty 1/3 duty s52 s53/osci 0 up to 200 segments up to 153 segments ?l? (v ss ) ?l? (v ss )/osci 1 up to 208 segments up to 159 segments s52 s53/osci note: ?l? (v ss ) : low (v ss ) level output s52 : segment output ?l? (v ss )/osci : low (v ss ) level output in internal oscillator operating mode (oc=0) : external clock input in external clock operating mode (oc=1) s53/osci : segment output in internal oscillator operating mode (oc=0) external clock input in external clock operating mode (oc=1)
LC75839PW no.a1953-15/27 (6) fc0 to fc2 ? common/segment output waveform fram frequency control data these control data bits set the frame frequency of the common and segment output waveforms. control data frame frequency fo[hz] fc0 fc1 fc2 internal oscillator operating mode (the control data oc is 0, fosc=300[khz]typ) external clock operating mode (the control data oc is 1 and exf is 0, f ck 1=300[khz]typ) external clock operating mode (the control data oc is 1 and exf is 1, f ck 2=38[khz]typ) 0 0 0 fosc/6144 f ck 1/6144 f ck 2/768 0 0 1 fosc/4608 f ck 1/4608 f ck 2/576 0 1 0 fosc/3072 f ck 1/3072 f ck 2/384 0 1 1 fosc/2304 f ck 1/2304 f ck 2/288 1 0 0 fosc/1536 f ck 1/1536 f ck 2/192 1 0 1 fosc/1152 f ck 1/1152 f ck 2/144 1 1 0 fosc/768 f ck 1/768 f ck 2/96 note: when is setting (fc0,fc1,fc2)=(1,1,1), the frame fre quency is same as frame frequency at the time of the (fc0,fc1,fc2)=(0,1,0) setting (fosc/3072, f ck 1/3072, f ck 2/384). (7) oc ? internal oscillator operating mode/external clock operating mode switching control data this control data bit selects either the internal oscillator operating mode or external clock operating mode. oc fundamental cl ock operating mode i/o pin (s53/osci) state 0 internal oscillator operating mode s53 1 external clock operating mode osci note: s53: segment output osci: external clock input (8) sc ? segment on/off control data this control data bit controls the on/off state of the segments. sc display state 0 on 1 off note that when the segments are turned off by setting sc to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. (9) bu ? normal mode/power-saving mode control data this control data bit selects either normal mode or power-saving mode. bu mode 0 normal mode 1 power saving mode in this mode, the internal oscillator circuit stops os cillation (the s53/osci pin is configured for segment output) if the ic is in the internal oscillator oper ating mode (oc=0) and the ic stops receiving external clock signals (the s53/osci pin is configured for exter nal clock input) if the ic is in the external clock operating mode (oc=1). the common and segment output pins go to the v ss level. however, the s1/p1 to s4/p4 output pins can be used as general-purpose output ports under the control of the data bits p0 to p2. (the general-purpose output port p1 to p4 ca n not be used as clock output or pwm output.)
LC75839PW no.a1953-16/27 (10) pf0 to pf3 ? pwm output waveform frame frequency setting control data these control data bits set the frame frequency of the pwm output waveforms. however, when the pwm output function isn?t used, these control data bits become invalid . in addition, when the external clock operating frequency is set the f ck 2=38[khz]typ (exf="1") in external clock operating mode (oc= "1"), these control data bits become invalid. control data pwm output waveform frame frequency fp[hz] pf0 pf1 pf2 pf3 internal oscillator operating mode (the control data oc is 0, fosc=300[khz] typ) external clock operating mode (the control data oc is 1 and exf is 0, f ck 1=300[khz] typ) 0 0 0 0 fosc/1536 f ck 1/1536 1 0 0 0 fosc/1408 f ck 1/1408 0 1 0 0 fosc/1280 f ck 1/1280 1 1 0 0 fosc/1152 f ck 1/1152 0 0 1 0 fosc/1024 f ck 1/1024 1 0 1 0 fosc/896 f ck 1/896 0 1 1 0 fosc/768 f ck 1/768 1 1 1 0 fosc/640 f ck 1/640 0 0 0 1 fosc/512 f ck 1/512 1 0 0 1 fosc/384 f ck 1/384 0 1 0 1 fosc/256 f ck 1/256 note: when is setting (pf0,pf1,pf2,pf3)=(1,1,0,1) and (x,x,1,1), the frame frequency is same as frame frequency at the time of the (pf0,pf1,pf2,pf3)=(1,0,1,0) setting (fosc/896, f ck 1/896). x: don?t care
LC75839PW no.a1953-17/27 (11) w10 to w15, w20 to w25, w30 to w35 ? pwm data of the pwm output these control data bits set the pulse width of the pwm output p1 to p4. however, when the pwm output function isn?t used, these control data bits become invalid. in additio n, when the external clock operating frequency is set the f ck 2=38[khz]typ (exf="1") in external clock operating mode (oc= "1"), these control data bits become invalid. wn0 wn1 wn2 wn3 wn4 wn5 pulse width of pwm output wn0 wn1 wn2 wn3 wn4 wn5 pulse width of pwm output 0 0 0 0 0 0 (1/64)tp 0 0 0 0 0 1 (33/64)tp 1 0 0 0 0 0 (2/64)tp 1 0 0 0 0 1 (34/64)tp 0 1 0 0 0 0 (3/64)tp 0 1 0 0 0 1 (35/64)tp 1 1 0 0 0 0 (4/64)tp 1 1 0 0 0 1 (36/64)tp 0 0 1 0 0 0 (5/64)tp 0 0 1 0 0 1 (37/64)tp 1 0 1 0 0 0 (6/64)tp 1 0 1 0 0 1 (38/64)tp 0 1 1 0 0 0 (7/64)tp 0 1 1 0 0 1 (39/64)tp 1 1 1 0 0 0 (8/64)tp 1 1 1 0 0 1 (40/64)tp 0 0 0 1 0 0 (9/64)tp 0 0 0 1 0 1 (41/64)tp 1 0 0 1 0 0 (10/64)tp 1 0 0 1 0 1 (42/64)tp 0 1 0 1 0 0 (11/64)tp 0 1 0 1 0 1 (43/64)tp 1 1 0 1 0 0 (12/64)tp 1 1 0 1 0 1 (44/64)tp 0 0 1 1 0 0 (13/64)tp 0 0 1 1 0 1 (45/64)tp 1 0 1 1 0 0 (14/64)tp 1 0 1 1 0 1 (46/64)tp 0 1 1 1 0 0 (15/64)tp 0 1 1 1 0 1 (47/64)tp 1 1 1 1 0 0 (16/64)tp 1 1 1 1 0 1 (48/64)tp 0 0 0 0 1 0 (17/64)tp 0 0 0 0 1 1 (49/64)tp 1 0 0 0 1 0 (18/64)tp 1 0 0 0 1 1 (50/64)tp 0 1 0 0 1 0 (19/64)tp 0 1 0 0 1 1 (51/64)tp 1 1 0 0 1 0 (20/64)tp 1 1 0 0 1 1 (52/64)tp 0 0 1 0 1 0 (21/64)tp 0 0 1 0 1 1 (53/64)tp 1 0 1 0 1 0 (22/64)tp 1 0 1 0 1 1 (54/64)tp 0 1 1 0 1 0 (23/64)tp 0 1 1 0 1 1 (55/64)tp 1 1 1 0 1 0 (24/64)tp 1 1 1 0 1 1 (56/64)tp 0 0 0 1 1 0 (25/64)tp 0 0 0 1 1 1 (57/64)tp 1 0 0 1 1 0 (26/64)tp 1 0 0 1 1 1 (58/64)tp 0 1 0 1 1 0 (27/64)tp 0 1 0 1 1 1 (59/64)tp 1 1 0 1 1 0 (28/64)tp 1 1 0 1 1 1 (60/64)tp 0 0 1 1 1 0 (29/64)tp 0 0 1 1 1 1 (61/64)tp 1 0 1 1 1 0 (30/64)tp 1 0 1 1 1 1 (62/64)tp 0 1 1 1 1 0 (31/64)tp 0 1 1 1 1 1 (63/64)tp 1 1 1 1 1 0 (32/64)tp 1 1 1 1 1 1 (64/64)tp note: w10 to w15 ? pwm data of the output pin s1/p1 and s4/p4 w20 to w25 ? pwm data of the output pin s2/p2 w30 to w35 ? pwm data of the output pin s3/p3 1 fp tp= n=1 to 3
LC75839PW no.a1953-18/27 display data and output pin correspondence (1/4 duty) output pin com1 com2 com3 com4 output pin com1 com2 com3 com4 s1/p1 d1 d2 d3 d4 s27 d105 d106 d107 d108 s2/p2 d5 d6 d7 d8 s28 d109 d110 d111 d112 s3/p3 d9 d10 d11 d12 s29 d113 d114 d115 d116 s4/p4 d13 d14 d15 d16 s30 d117 d118 d119 d120 s5 d17 d18 d19 d20 s31 d121 d122 d123 d124 s6 d21 d22 d23 d24 s32 d125 d126 d127 d128 s7 d25 d26 d27 d28 s33 d129 d130 d131 d132 s8 d29 d30 d31 d32 s34 d133 d134 d135 d136 s9 d33 d34 d35 d36 s35 d137 d138 d139 d140 s10 d37 d38 d39 d40 s36 d141 d142 d143 d144 s11 d41 d42 d43 d44 s37 d145 d146 d147 d148 s12 d45 d46 d47 d48 s38 d149 d150 d151 d152 s13 d49 d50 d51 d52 s39 d153 d154 d155 d156 s14 d53 d54 d55 d56 s40 d157 d158 d159 d160 s15 d57 d58 d59 d60 s41 d161 d162 d163 d164 s16 d61 d62 d63 d64 s42 d165 d166 d167 d168 s17 d65 d66 d67 d68 s43 d169 d170 d171 d172 s18 d69 d70 d71 d72 s44 d173 d174 d175 d176 s19 d73 d74 d75 d76 s45 d177 d178 d179 d180 s20 d77 d78 d79 d80 s46 d181 d182 d183 d184 s21 d81 d82 d83 d84 s47 d185 d186 d187 d188 s22 d85 d86 d87 d88 s48 d189 d190 d191 d192 s23 d89 d90 d91 d92 s49 d193 d194 d195 d196 s24 d93 d94 d95 d96 s50 d197 d198 d199 d200 s25 d97 d98 d99 d100 s52 d201 d202 d203 d204 s26 d101 d102 d103 d104 s53/ osci d205 d206 d207 d208 note: this table assumes that pins s1/p1 to s4/p4 and s53/osci are configured for segment output. for example, the table below lists the output states for the s21 output pin. display data d81 d82 d83 d84 output pin (s21) state 0 0 0 0 the lcd segments corresponding to com1, com2, com3, and com4 are off. 0 0 0 1 the lcd segment corresponding to com4 is on. 0 0 1 0 the lcd segment corresponding to com3 is on. 0 0 1 1 the lcd segments corresponding to com3 and com4 are on. 0 1 0 0 the lcd segment corresponding to com2 is on. 0 1 0 1 the lcd segments corresponding to com2 and com4 are on. 0 1 1 0 the lcd segments corresponding to com2 and com3 are on. 0 1 1 1 the lcd segments corresponding to com2, com3, and com4 are on. 1 0 0 0 the lcd segment corresponding to com1 is on. 1 0 0 1 the lcd segments corresponding to com1 and com4 are on. 1 0 1 0 the lcd segments corresponding to com1 and com3 are on. 1 0 1 1 the lcd segments corresponding to com1, com3, and com4 are on. 1 1 0 0 the lcd segments corresponding to com1 and com2 are on. 1 1 0 1 the lcd segments corresponding to com1, com2, and com4 are on. 1 1 1 0 the lcd segments corresponding to com1, com2, and com3 are on. 1 1 1 1 the lcd segments corresponding to com1, com2, com3, and com4 are on.
LC75839PW no.a1953-19/27 display data and output pin correspondence (1/3 duty) output pin com1 com2 com3 output pin com1 com2 com3 s1/p1 d1 d2 d3 s28 d82 d83 d84 s2/p2 d4 d5 d6 s29 d85 d86 d87 s3/p3 d7 d8 d9 s30 d88 d89 d90 s4/p4 d10 d11 d12 s31 d91 d92 d93 s5 d13 d14 d15 s32 d94 d95 d96 s6 d16 d17 d18 s33 d97 d98 d99 s7 d19 d20 d21 s34 d100 d101 d102 s8 d22 d23 d24 s35 d103 d104 d105 s9 d25 d26 d27 s36 d106 d107 d108 s10 d28 d29 d30 s37 d109 d110 d111 s11 d31 d32 d33 s38 d112 d113 d114 s12 d34 d35 d36 s39 d115 d116 d117 s13 d37 d38 d39 s40 d118 d119 d120 s14 d40 d41 d42 s41 d121 d122 d123 s15 d43 d44 d45 s42 d124 d125 d126 s16 d46 d47 d48 s43 d127 d128 d129 s17 d49 d50 d51 s44 d130 d131 d132 s18 d52 d53 d54 s45 d133 d134 d135 s19 d55 d56 d57 s46 d136 d137 d138 s20 d58 d59 d60 s47 d139 d140 d141 s21 d61 d62 d63 s48 d142 d143 d144 s22 d64 d65 d66 s49 d145 d146 d147 s23 d67 d68 d69 s50 d148 d149 d150 s24 d70 d71 d72 s51/com4 d151 d152 d153 s25 d73 d74 d75 s52 d154 d155 d156 s26 d76 d77 d78 s53/osci d157 d158 d159 s27 d79 d80 d81 note: this table assumes that pins s1/p1 to s4/p4, s5 1/com4, and s53/osci are configured for segment output. for example, the table below lists the output states for the s21 output pin. display data d61 d62 d63 output pin (s21) state 0 0 0 the lcd segments corresponding to com1, com2, and com3 are off. 0 0 1 the lcd segment corresponding to com3 is on. 0 1 0 the lcd segment corresponding to com2 is on. 0 1 1 the lcd segments corresponding to com2 and com3 are on. 1 0 0 the lcd segment corresponding to com1 is on. 1 0 1 the lcd segments corresponding to com1 and com3 are on. 1 1 0 the lcd segments corresponding to com1 and com2 are on. 1 1 1 the lcd segments corresponding to com1, com2, and com3 are on.
LC75839PW no.a1953-20/27 output waveforms (1/4-duty 1/3-bias drive scheme) control data frame frequency fo[hz] fc0 fc1 fc2 internal oscillator operating mode (the control data oc is 0, fosc=300[khz]typ) external clock operating mode (the control data oc is 1 and exf is 0, f ck 1=300[khz]typ) external clock operating mode (the control data oc is 1 and exf is 1, f ck 2=38[khz]typ) 0 0 0 fosc/6144 f ck 1/6144 f ck 2/768 0 0 1 fosc/4608 f ck 1/4608 f ck 2/576 0 1 0 fosc/3072 f ck 1/3072 f ck 2/384 0 1 1 fosc/2304 f ck 1/2304 f ck 2/288 1 0 0 fosc/1536 f ck 1/1536 f ck 2/192 1 0 1 fosc/1152 f ck 1/1152 f ck 2/144 1 1 0 fosc/768 f ck 1/768 f ck 2/96 note: when is setting (fc0,fc1,fc2)=(1,1,1), the frame fre quency is same as frame frequency at the time of the (fc0,fc1,fc2)=(0,1,0) setting (fosc/3072, f ck 1/3072, f ck 2/384). com3 com2 com1 com4 lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are on. lcd driver output when lcd segments corresponding to com2 and com4 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com1, com2, and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are off. v dd 1 v dd 2 fo[hz] v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v
LC75839PW no.a1953-21/27 output waveforms (1/3-duty 1/3-bias drive scheme) control data frame frequency fo[hz] fc0 fc1 fc2 internal oscillator operating mode (the control data oc is 0, fosc=300[khz]typ) external clock operating mode (the control data oc is 1 and exf is 0, f ck 1=300[khz]typ) external clock operating mode (the control data oc is 1 and exf is 1, f ck 2=38[khz]typ) 0 0 0 fosc/6144 f ck 1/6144 f ck 2/768 0 0 1 fosc/4608 f ck 1/4608 f ck 2/576 0 1 0 fosc/3072 f ck 1/3072 f ck 2/384 0 1 1 fosc/2304 f ck 1/2304 f ck 2/288 1 0 0 fosc/1536 f ck 1/1536 f ck 2/192 1 0 1 fosc/1152 f ck 1/1152 f ck 2/144 1 1 0 fosc/768 f ck 1/768 f ck 2/96 note: when is setting (fc0,fc1,fc2)=(1,1,1), the frame fre quency is same as frame frequency at the time of the (fc0,fc1,fc2)=(0,1,0) setting (fosc/3072, f ck 1/3072, f ck 2/384). v dd 2 v dd 1 v dd 0v v dd 2 v dd 1 v dd 0v v dd 2 v dd 1 v dd 0v v dd 2 v dd 1 v dd 0v v dd 2 v dd 1 v dd 0v v dd 2 v dd 1 v dd 0v v dd 2 v dd 1 v dd 0v v dd 2 v dd 1 v dd 0v v dd 2 v dd 1 v dd 0v v dd 2 v dd 1 v dd 0v v dd 2 v dd 1 0v fo [ hz ] v dd com3 com2 com1 lcd driver output when all lcd segments corresponding to com1, com2, and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when all lcd segments corresponding to com1, com2, and com3 are off.
LC75839PW no.a1953-22/27 pwm output waveforms control data w10 w11 w12 w13 w14 w15 w20 w21 w22 w23 w24 w25 w30 w31 w32 w33 w34 w35 pwm output waveforms 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 (1) 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 (2) 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 (3) note: when is setting (pf0,pf1,pf2,pf3)=(1,1,0,1) and (x,x,1,1 ), the frame frequency is same as frame frequency at the time of the (pf0,pf1,pf2,pf3)=(1,0,1,0) setting (fosc/896, f ck 1/896). x: don?t care control data pwm output waveform frame frequency fp[hz] pf0 pf1 pf2 pf3 internal oscillator operating mode (the control data oc is 0, fosc=300[khz] typ) external clock operating mode (the control data oc is 1 and exf is 0, f ck 1=300[khz] typ) 0 0 0 0 fosc/1536 f ck 1/1536 1 0 0 0 fosc/1408 f ck 1/1408 0 1 0 0 fosc/1280 f ck 1/1280 1 1 0 0 fosc/1152 f ck 1/1152 0 0 1 0 fosc/1024 f ck 1/1024 1 0 1 0 fosc/896 f ck 1/896 0 1 1 0 fosc/768 f ck 1/768 1 1 1 0 fosc/640 f ck 1/640 0 0 0 1 fosc/512 f ck 1/512 1 0 0 1 fosc/384 f ck 1/384 0 1 0 1 fosc/256 f ck 1/256 1 fp tp= (56/64) tp p1/p4 v dd v ss (48/64) tp p2 v ss v dd (40/64) tp p3 v ss v dd (1) (32/64) tp p1/p4 v dd v ss (32/64) tp p2 v ss v dd (32/64) tp p3 v ss v dd (3) (8/64) tp (8/64) tp p1/p4 v dd v ss (16/64) tp p2 v ss v dd (24/64) tp p3 v ss v dd (2) (16/64) tp (24/64) tp (32/64) tp (32/64) tp (32/64) tp tp tp (56/64) tp (48/64) tp (40/64) tp
LC75839PW no.a1953-23/27 clock output waveforms control data ps10 ps11 clock frequency of clock output p1 fc(=1/tc)[hz] 1 0 clock output function (fosc/2, f ck /2) 0 1 clock output function (fosc/8, f ck /8) p1 tc tc/2 1 fc tc=
LC75839PW no.a1953-24/27 display control and the inh pin since the lsi internal data (1/4 duty : the display data d1 to d208 and the control data, 1/3 duty : the display data d1 to d159 and the control data) is undefined when power is first applied, applications should set the inh pin low at the same time as power is applied to turn off the display (this sets the s1/p1 to s4/p4, s5 to s50, com1 to com3, com4/s51, s52, and s53/osci pins to the v ss level.) and during this peri od send serial data from the controller. the controller should then set the inh pin high after the data transfer has completed. this procedure prevents meaningless display at power on. (see figure 5, figure 6.) (1)1/4 duty (2)1/3 duty defined notes: t1 > 1ms t2 > 0 tc?10 s min display data and control data transferred v dd t2 undefined undefined ce inh undefined undefined defined [figure 5] undefined v il 1 tc v il 1 internal data (d153 to d208) d1 to d52,ps10,ps11, exf,p0 to p2,dt,dn, fc0 to fc2,oc,sc,bu internal data t1 defined defined defined undefined undefined undefined display data and control data transferred v dd t2 ce inh undefined [figure 6] undefined v il 1 tc v il 1 t1 undefined undefined defined defined undefined undefined notes: t1 > 1ms t2 > 0 tc?10 s min d53 to d104,ps2 to ps4, pf0 to pf3 internal data d105 to d152,w10 to w15, w20 to w25, w30 to w35 internal data d1 to d54,ps10,ps11, exf,p0 to p2,dt,dn, fc0 to fc2,oc,sc,bu internal data d55 to d108,ps2 to ps4, pf0 to pf3 internal data d109 to d159,w10 to w15, w20 to w25, w30 to w35 internal data
LC75839PW no.a1953-25/27 notes on controller transf er of display data when using the lc75839 in 1/4 duty, applications transfer the display data (d1 to d208) in four operations, and in 1/3 duty, they transfer the display data (d1 to d159) in three op erations. in either case, applications should transfer all of the display data within 30 ms to maintain the quality of displayed image. s53/osci pin peripheral circuit (1) internal oscillator operating mode (control data oc=0) connect the s53/osci pin to the lcd panel when the internal oscillator operating mode is selected. (2) external clock operating mode (control data oc=1) when the external clock operating m ode is selected, insert a current pr otection resistor rg (2.2 to 22k ) between the s53/osci pin and external clock output pin (external oscillator). determine the value of the resistance according to the allowable current value at the ex ternal clock output pin. also make sure that the waveform of the external clock is not heavily distorted. (3) unused pin treatment when the s53/osci pin is not to be used, select the intern al oscillator operating mode (setting control data oc to 0) to keep the pin open. p1 to p4 pin peripheral circuit it is recommended the circuit shown below be used to adjust the brightness of the led backlight using the pwm output p1 to p4 osci/s53 external clock output pin rg external oscillato r note: allowable current value at external clock output pin > v dd rg osci/s53 to lcd panel osci/s53 open p1 to p4 led +5v
LC75839PW no.a1953-26/27 sample applications circuit1 1/4 duty, 1/3 bias * 2 the pins to be connected to the controller (ce, cl, di, inh ) can handle 3.3v or 5v. * 3 connect the s53/osci pin to the lcd panel in the internal oscillator operating mode and insert a current protection resistor rg (2.2 to 22k ) between the s53/osci pin and external clock output pin (external oscillator) in the external clock operating mode (see ?s 53/osci pin peripheral circuit?). sample application circuit 2 1/3 duty, 1/3 bias * 2 the pins to be connected to the controller (ce, cl, di, inh ) can handle 3.3v or 5v. * 3 connect the s53/osci pin to the lcd panel in the internal oscillator operating mode and insert a current protection resistor rg (2.2 to 22k ) between the s53/osci pin and external clock output pin (external oscillator) in the external clock operating mode (see ?s 53/osci pin peripheral circuit?). used for functions such as backlight control general-purpose output ports (p4) (p2) (p1) lcd panel (up to 208 segments) di cl ce inh v dd 1 osci/s53 s51/com4 s52 s5 p4/s4 p2/s2 p1/s1 com3 com2 com1 *2 v dd v dd 2 v ss c from the controller c 0.047 0.047
LC75839PW no.a1953-27/27 ps this catalog provides information as of june, 2011. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rat ed values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that c ould endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descr ibed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any oth er rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from th e use of the technical information and products mentioned above. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export contro l laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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